50.002 Computation Structures

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Course Description

This course introduces architecture of digital systems, emphasising structural principles common to a wide range of technologies. Topics include Multilevel implementation strategies; definition of new primitives (e.g., gates, instructions, procedures, and processes) and their mechanisation using lower-level elements. Analysis of potential concurrency; precedence constraints and performance measures; pipelined and multidimensional systems; instruction set design issues; architectural support for contemporary software structures.


Learning Objectives

  1. State the role of abstraction in the design of large digital systems, and explain the major software and hardware abstractions in contemporary computer systems.
  2. Design simple hardware systems based on a variety of digital abstractions such as ROMs, logic arrays and state machines.
  3. Synthesize digital systems from a library of representative components and test the designs under simulation.
  4. Describe the operation of a moderately complex digital system — a simple RISC-based computer — down to the gate level, and be able to specify, implement and debug its components.
  5. Appreciate the technical skills necessary to be a capable digital systems engineer.
  6. Explain the fundamentals of modern operating systems.

Measurable Outcomes

  1. Identify flaws and limitations in simple systems implemented using the static discipline.
  2. Identify flaws and limitations in simple systems implemented using clocked registers with asynchronous inputs.
  3. Identify flaws and limitations in simple systems implemented using semaphores for process synchronization.
  4. Characterize the logic function of combinational devices using CMOS, ROM or PLA technologies.
  5. Explain synthesis issues for combinational devices using CMOS, ROM or PLA technologies from their functional specification.
  6. Explain synthsis of acyclic circuits from combinational components.
  7. Calculate performance characteristics of acyclic circuits with combinational components.
  8. Explain and calculate performance characteristics of single-clock sequential circuits.
  9. Implement a simple RISC-based CPU architecture.
  10. Explain the underlaying theory of memory hierarchy.
  11. Implement a device handler using interrupt and SVC.
  12. Implement a synchronization system for processes using semaphore.

Topics Covered

  • Course overview and mechanics, Basics of Information
  • The Digital Abstraction, CMOS Technology
  • Basic Hardware Lab (Combine with EPD)
  • Logic Synthesis
  • Logic Simplification, Multiplexer, ROM
  • SW Lab1 (CMOS)
  • Sequential Logic
  • Finite State Machines and Synchronization
  • SW Lab 2 (Adder)
  • Computers and Programs
  • The Assembly Language
  • SW Lab 3 (ALU)
  • The C language, Stacks and Procedures
  • Stacks and Procedures (II)
  • Building the Beta
  • Building the Beta (II)
  • SW Lab 5 (Assembly Language)
  • Memory Hierarchy
  • Cache Issues
  • SW Lab 6 (Beta)
  • Virtual Memory
  • Virtual Machines
  • SW Lab 6 (Beta)
  • Device Handlers and Bus
  • Processes, Synchronization, and Deadlock, OS summary
  • SW Lab 8 (Tiny OS)

Textbook(s) and/or Other Required Material

  • Stephen A. Ward, Robert H. Halstead, Computation Structures (The MIT Electrical Engineering and Computer Science Series). Cambridge, MA: MIT Press. 1999.

Course Instructor(s)

Prof Natalie Agus, Prof Wang Bo, Prof Felix Loh