Angela Wang Bo

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Assistant Professor

Email: 
Office #: 1.602-18
Pillar / Cluster: Information Systems Technology and Design
Research Areas:Artificial and Augmented Intelligence, , Networked and Autonomous Systems

Biography

Dr. Wang Bo, Angela is an Assistant Professor at SUTD since September 2020. Her research interests span various aspects of energy-efficient computing systems, architecture and circuit design, including on-device artificial intelligence, neuromorphic computing, biomedical wearables and ultra-low voltage memories. Her research work was featured by The Straits Times in 2020 and filed as a Singapore patent. She was the recipient of IEEE Circuits & Systems Seoul Chapter Award in 2014.

Dr. Wang received her Ph.D. degree from Nanyang Technological University in 2015. Prior to joining SUTD, she was a research fellow with the Department of Computer Science at National University of Singapore. She is an IEEE senior member.

Selected Publications

  • “Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip”, by B. Wang, J. Zhou, W. Wong and L. Peh. Design, Automation and Test in Europe Conference, Mar. 2020.
  • “HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications” by B. Wang, M. Karunaratne, A. Kulkarni, T. Mitra and L. Peh. IEEE Asian Solid-State Circuits Conference, Nov. 2019.
  • “pH Watch – Leveraging Pulse Oximeters in Existing Wearables for Reusable, Real-time Monitoring of pH in Sweat” by A. Balaji, C. Yuan, B. Wang, L. Peh and H. Shao. International Conference on Mobile Systems, Applications, and Services, Jun. 2019.
  •  “A 0.4V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance” by B. Wang, J. Zhou, and T. Kim. Microelectronics Journal, vol 69, no. 11, 2017.
  • “Read bitline sensing and fast local write-back techniques in hierarchical bitline architecture for ultra-low voltage SRAMs” by B. Wang, Q. Li, and T. Kim. IEEE Transactions on Very Large Scale Integration Systems, vol 24, no. 6, 2016.
  • “Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement” by B. Wang, T. Q. Nguyen, A. Do, J. Zhou. M. Je, and T. Kim. IEEE Transactions on Circuits and Systems-I, vol 62, no. 2, 2015.
  • “SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS” by B. Wang, J. Zhou, and T. Kim. Microelectronics Journal, vol 46, no. 3, 2015.
  • “A 457-nW near-threshold cognitive multi-functional ECG processor CMOS for long-term cardiac monitoring” by X. Liu, J. Zhou, Y. Yang, B. Wang, J. Lan, C. Wang, J. Luo, W. L. Goh, T. Kim, and M. Je. IEEE Journal of Solid-State Circuits, vol 49, no. 11, 2014.
  • “0.2V 8T SRAM with Improved Bitline Sensing Using Column-based Data Randomization” by A. Do, Z. Lee, B. Wang, I. Chang, and T. Kim. IEEE Asian Solid-State Circuits Conference, Nov. 2014.
  • “A 0.5V 29pJ/Cycle Sensor Node Processor for Intelligent Sensing Applications” by J. Zhou, X. Liu, C. Wang, K. Chang, J. Luo, J. Lan, L. Liao, Y. Lam, Y. Yang, B. Wang, X. Zhang, W. Goh, T. Kim, and M. Je. International SoC Design Conference, Nov. 2014.
  • “A 0.18V charge-pumped DFF with 50.8% energy-delay reduction for near-/sub-threshold circuits” by B. Wang, J. Zhou, K. H. Chang, M. Je, and T. Kim. IEEE Asian Solid-State Circuits Conference, Nov. 2013.
  • “A 457-nW Cognitive Multi-Functional ECG Processor” by X. Liu, J. Zhou, Y. Yang, B. Wang, J. Lan, C. Wang, J. Luo, W. L. Goh, T. Kim, and M. Je. IEEE Asian Solid-State Circuits Conference, Nov. 2013.
  • “A 0.4V 7T SRAM with Write Through Virtual Ground and Ultra-fine Grain Power Gating Switches” by Y. Yeoh, B. Wang, X Yu, and T. Kim. IEEE International Symposium on Circuits and Systems, May 2013.
  • “A 0.2V 16Kb 9T SRAM with bitline leakage equalization and CAM-assisted write performance boosting for improving energy efficiency” by B. Wang, T. Q. Nguyen, A. Do, J. Zhou. M. Je, and T. Kim. IEEE Asian Solid-State Circuits Conference, Nov. 2012.
  • “High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture” by T. Kim, B. Wang, and A. Do. International SoC Design Conference, Nov. 2012.
  • “A 5.61 pJ, 16 kb 9T SRAM with Single-ended Equalized Bitlines and Fast Local Write-back for Cell Stability Improvement” by Q. Li, B. Wang, and T. Kim. IEEE European Solid-State Device Research Conference, Sep. 2012.
  • “Maximization of SRAM Energy Efficiency Utilizing MTCMOS Technology” by B. Wang, J. Zhou, and T. Kim. Asia Symposium on Quality Electronic Design, Jul. 2012.

Research Interest

  1. Architectures and Circuits of Neuromorphic Computing
  2. Energy-Efficient AI for Edge Computing Systems

Research Positions

  • Research Associate Positions on Neuromorphic Computing Acceleration
  • Ph.D Scholarship available for Singaporean or SPR on Energy-Efficient on-chip AI
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